High speed PCB design rules and the reason analysis

1.PCB clock frequency more than 5 MHZ or signal rise time is less than 5 ns, generally need to use a multilayer design.

Reason: the sandwich plate design signal circuit area can get good control.

2.for the sandwich plate, the key wiring layer (the clock line, bus, interface signal and rf line and reset signal lines, choose line and all kinds of control signal wire layer) and completely flat, adjacent optimization between two plane.

Reason: the key signal lines are generally strong radiation or extremely sensitive line, close to the ground plane wiring can reduce its signal loop area, reduce the radiation intensity or improve the anti-interference ability. `

3. for single layer plate, the key should be pack on both sides of signal processing.